1. Field of the Invention
The present invention relates to semiconductor assemblies, and more particularly, to a semiconductor assembly having a laminated layer structure of a plurality of semiconductor devices.
2. Description of the Related Art
In semiconductor integrated circuit devices, the degree of integration of the circuit has been increasing, and the number of pads for supplying input/output signals and a power supply voltage becomes very great while high operational speed is required.
In electronic apparatus, particularly, in personal computers and large-scale computers, the mounting area of such semiconductor devices has been increasing. This increased mounting area has been a problem in the miniaturization of the apparatus.
For the purpose of avoiding the above problem, such measures have been taken as to increase the integration degree in which elements are arranged within a chip, and after packaging the chips, mounting the packages on a printed circuit board at a high density.
Conventionally, these packages of chips, such as surface mounting type semiconductor devices, are arranged on the surface of a printed circuit board out and the leads of the devices are connected to signal wiring lines on the printed circuit board.
Such a conventional mounting technique, however, has such a problem that, since the surface mounting type semiconductor devices are mounted on the surface plane in parallel or in a matrix form, it is impossible to remarkably reduce the mounting area for the devices.